The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimensions of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions of less than 1,000 xc3x85, e.g., less than 800 xc3x85, are required for acceptable performance in short channel devices.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silicide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Desirably, the metal silicide is only formed on the underlying silicon, not on the dielectric sidewall spacers. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the xe2x80x9csalicidexe2x80x9d process.
A portion of a typical semiconductor device 10 is schematically illustrated in FIG. 1 and comprises a silicon-containing substrate 12 with shallow source/drain extensions 15A and source/drain 15B regions formed therein. Gate oxide 24 and gate electrode 28 are formed on the silicon-containing substrate 12. Sidewall spacers 18 are formed on opposing side surfaces 29 of gate electrode 28. Sidewall spacers 18 typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers 18 function to mask shallow source/drain extensions 15A during ion implantation to form source/drain regions 15B. The sidewall spacers 18 also mask the side surfaces 29 of the gate 28 when metal layer 16 is deposited, thereby preventing silicide from forming on the side surfaces 29.
After metal layer 16 is deposited, heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode and substrate surface to form conductive metal silicide contacts 26. After the metal silicide contacts 26 are formed, the unreacted metal 16 is removed by etching, as with a wet etchant, e.g., an aqueous H2O2/NH4OH solution. The sidewall spacer 18, therefore, acts as an electrical insulator separating the silicide contact 26 on the gate electrode 28 from the metal silicide contacts 26 on the source/drain regions 15B, as shown in FIG. 2.
Difficulties are encountered in such a conventional silicidation process, particularly when employing silicon nitride sidewall spacers and nickel as the metal. Specifically it was found that nickel reacts with dangling silicon bonds in the silicon nitride sidewall spacers during heating to form nickel silicide layers on the sidewall spacer surface 20 forming an electrical bridge between the nickel silicide contact 26 on the gate electrode 28 and the nickel silicide contact 26 on the source/drain regions 15B. This undesirable effect is particularly problematic as device design rules plunge into the deep sub-micron range and is schematically illustrated in FIG. 3, wherein sidewall spacer surface 20 contains dangling silicon bonds 21. When the metal layer 16 is deposited on the sidewall spacer surface 20 and heated, a metal silicide layer 26 remains on the surface of the sidewall spacer 20 after etching.
Bridging between the gate electrode and the associated source/drain regions results in diminished device performance and device failure.
Additional difficulties encountered in the silicidation process include oxidation of the gate electrode and source/drain surfaces. Surface oxides on the gate electrode and source/drain regions can inhibit the silicidation reaction between the metal and silicon. Metals that can not diffuse through a silicon oxide surface film, such as titanium, will not readily react with the underlying silicon when heated, resulting in inadequate metal silicide formation. Surface oxides readily form on exposed silicon surfaces under ambient environmental conditions. Aqueous HF is conventionally used to remove surface oxides prior to depositing the silicidation metal. However, if the metal layer is not deposited in a timely manner after HF treatment, the surface oxide layer will be regenerated, requiring additional HF treatment. In addition, the use of aqueous HF to remove surface oxide films from the gate and source and drain regions also undesirably removes surface Oxides and leaves dangling silicon bonds on the sidewall spacers.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chip, flip chip/package assemblies, transistors, capacitors, microprocessors,random access memories, etc. In general, se comprising semiconductors.
There exists a need for efficient methodology to produce highly reliable semiconductor devices with ultra-shallow junctions by eliminating bridging between transistor gate electrodes and associated source/drain regions and preventing surface oxidation of gate electrodes and source/drain regions. There exists a particular need in this art to eliminate nickel silicide formation on silicon nitride sidewall spacer surfaces.
These and other needs are met by the embodiments of the present invention, which provide a method of passivating a semiconductor device comprising: providing an intermediate product comprising a gate electrode on a semiconductor substrate with a gate insulating layer therebetween. The gate electrode has an upper surface and opposing side surfaces. The intermediate product is contacted with a solution comprising iodine and ethanol for a period of time sufficient to passivate surface regions of the intermediate product.
The earlier stated needs are also met by another embodiment of the instant invention which provides a method of manufacturing a semiconductor device comprising forming silicide contacts on a semiconductor device comprising: providing an intermediate product comprising a gate electrode and source/drain regions, wherein sidewall spacers are formed on the side surfaces of the gate electrode. The surfaces of the intermediate product are contacted with an iodine and ethanol solution for a period of time sufficient to passivate the surfaces of the intermediate product. A metal layer is deposited over the intermediate product and the metal layer is subsequently heated at a temperature sufficient to cause the metal to react with silicon in the gate electrode and source/drain regions to form metal silicide. Unreacted metal is subsequently removed from the intermediate product.
The earlier stated needs are further met by another embodiment of the instant invention that provides a semiconductor device comprising a gate electrode on a semiconductor substrate with a gate insulating layer therebetween. The gate electrode has an upper surface and opposing side surfaces. The surfaces of the semiconductor device are passivated by contacting them with an iodine and ethanol solution.
The foregoing other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with, the accompanying drawings.